Logic gates: labelled reference, US style

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Logic gates: labelled reference, US style, sheet 1 of 1

  1. Fig. 1

    ABY

    AND gate

    An AND gate's output is 1 only when every input is 1.

  2. Fig. 2

    ABY

    OR gate

    An OR gate's output is 1 when any input is 1.

  3. Fig. 3

    AY

    NOT gate

    A NOT gate's output is the opposite of its input.

  4. Fig. 4

    ABY

    NAND gate

    A NAND gate's output is 0 only when every input is 1.

  5. Fig. 5

    ABY

    NOR gate

    A NOR gate's output is 1 only when every input is 0.

  6. Fig. 6

    ABY

    XOR gate

    An exclusive-OR gate's output is 1 when its two inputs differ.

Terminal key
Fig.TerminalsWhat the terminal is
1–6A, BIn the unrotated gate drawings here, inputs appear on the left. Each input is a logic value, 0 or 1; rotating the symbol does not turn an input into an output.
1–6YIn the unrotated gate drawings here, the output appears on the right. Its settled logic value follows the gate's truth table.

Sources

  1. ModEL — Semiconductor Logic Gates, §3.1 (truth tables, pp. 34–35), Tony R. Kuphaldt, retrieved 2026-09-22
  2. Overview of IEEE Standard 91-1984 — Explanation of Logic Symbols, §§2–3 (pp. 2–5), Texas Instruments, retrieved 2026-09-22
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Logic gates Labelled reference
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US style
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