Logic gates: naming exercise and answer key, IEC style

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Logic gates: naming exercise, IEC style, sheet 1 of 2

  1. Fig. 1

    Name

    Meaning

  2. Fig. 2

    Name

    Meaning

  3. Fig. 3

    Name

    Meaning

  4. Fig. 4

    Name

    Meaning

  5. Fig. 5

    Name

    Meaning

  6. Fig. 6

    Name

    Meaning

Notes

  1. Write the name of each symbol, and what it shows, on its lines.
  2. Write the name of each terminal in its box.
  3. The answers are on sheet 2.
Name
Class
Date
Sheet
1 of 2
Drawing
Logic gates Naming exercise
Style
IEC style
From
circuitsymbols.com
Licence
CC BY 4.0

Logic gates: answer key, IEC style, sheet 2 of 2

  1. Fig. 1

    ABY

    Name AND gate

    An AND gate's output is 1 only when every input is 1.

  2. Fig. 2

    ABY

    Name OR gate

    An OR gate's output is 1 when any input is 1.

  3. Fig. 3

    AY

    Name NOT gate

    A NOT gate's output is the opposite of its input.

  4. Fig. 4

    ABY

    Name NAND gate

    A NAND gate's output is 0 only when every input is 1.

  5. Fig. 5

    ABY

    Name NOR gate

    A NOR gate's output is 1 only when every input is 0.

  6. Fig. 6

    ABY

    Name XOR gate

    An exclusive-OR gate's output is 1 when its two inputs differ.

Notes

  1. Answer key for sheet 1. The Fig. numbers match the exercise.
Name
Class
Date
Sheet
2 of 2
Drawing
Logic gates Answer key
Style
IEC style
From
circuitsymbols.com
Licence
CC BY 4.0